Signed Binary Addition Circuitry with Inherent Even Parity Outputs |
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other possible signed binary addition tables that exhibit this prop- erty. An entire class of new addition tables is discussed with some specific examples given. While this class of addition tables is useful for building high speed addition circuitry, the redundancy inherent in the data words can also be used for error detection purposes. It is shown that an addition circuit can be constructed that utilizes S BD re- dundancy for both the purpose of constructing a high speed addi- tion circuit and to always generate sums that have even parity. This characteristic incorporates a fault detection characteristic without adversely affecting the parallelism needed for high speed operation. This approach has the advantage that no extra parity bits are generated, the bits representing the sum value itself are all that are present. In general, SBD adders pay the implementation price of an in- creased area requirement in order to achieve a decreased delay characteristic. Furthermore, the resulting sum is in S BD form re- quiring a conversion to twos complement or some other form in- curring the delay of an extra addition stage since the sum is typi- cally separated into a negative and positive value, then combined using a more traditional adder. For these reasons, S BD addition circuits are generally not considered to be useful as standalone adders. However, in the case of accumulation of more than two operands, such as partial product accumulation in a multiplier circuit, SBD circuits offer distinct advantages. As described in [17], [6], trees of 3:2, 7:3, and 15:4 counters al- low for the sum of several operands to be formulated while incur- ring the cost of a single carry-propagation stage (or an equivalent addition circuit) only in the final level of the addition tree. In the tree-based schemes for partial product accumulation, the overall delay is dependent upon the number of levels of constant delay adders. The number of levels can be decreased by using SBD add- ers with reduction rates of 2:1 instead of the 3:2 counters used in [17]. This fact is responsible for the use of SBD adders in commer- cial products such as the one described in [4]. The central justification for the pursuit of the results described in this paper is to refine the SBD addition circuit which is the basis of some commercially produced integrated circuits. In particular, it is shown that an entire family of addition tables may be used as a basis for these circuits. Furthermore, exploitation of the redun- dancy inherent in the encoding of the operands such that they are represented using the digit set { , , } 1 0 1 may be used to incorporate |
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